1. Field of the Invention
The present invention is related generally to integrated circuits, and more specifically to circuits included on integrated circuit devices for testing purposes.
2. Description of the Prior Art
It is usually desirable to increase the number of logical functions performed on a single integrated circuit chip. This allows for the replacement of several integrated circuit devices by a single device, thereby decreasing system cost. Other benefits also accrue, typically including lower system power consumption and improved performance.
Custom chip design is relatively expensive, and design changes are often difficult. Of increasing popularity within the electronics industry has been the use of integrated circuit chips which are programmable by the system designer or end user. These devices are referred to generally as programmable logic devices (PLDs). With these devices, the user can tailor operation of a general purpose commodity device to his specific needs.
One common type of PLD includes an AND-OR array. This array is programmed to provide desired logic functions. Programmable input and output buffers are also provided on many such devices. A programmable logic device is configured by writing data into architecture bits, also known as configuration bits, on the chip. These bits are used to select from various functions which are available on the device.
Configuration bits can be used, for example, to define a pin on an integrated circuit chip as an output pin or an input pin. An input or output pin can be defined as active high or active low. In general, the configuration bits are used to program the behavior of the programmable logic device. These bits are stored on the chip in non-volatile memory. Since the configuration information is written into non-volatile memory, it can be written to the chip by the user, and the chip will retain its desired configuration.
The configuration bits allow the programmable logic device to be programmed to operate in any of several configurations. Chip manufacturers prefer to test all possible configurations to ensure proper chip function before shipping the completed devices to users and resellers. This means that, during testing, the configuration bits must be reprogrammed for each possible configuration. Typically, all configuration bits must be cleared prior to programming a new configuration to be tested.
The configuration information is typically stored in EEPROM, although EPROMs and PROMs are also used. With EEPROMs, clear and program times are typically on the order of a few milliseconds. This means that, for example, 30-50 ms would be needed just to reprogram the configuration bits on a device having 9 or 10 different configurations.
The delay inherent in programming the configuration bits adds greatly to the total time required for chip testing. This adds to the overall cost of the programmable logic device. If it is necessary to minimize cost and tester time, it is sometimes necessary to test only a few of the possible configurations of each device.
It would be desirable to provide a mechanism which minimized test time while still allowing full testability of all device configurations. It is also desirable that such a mechanism does not adversely effect normal configuration programming and operation of the device.